The present invention relates to analog-to-digital conversion, and more particularly, to an apparatus for applying different transfer functions to code segments of a multi-bit output code that are sequentially determined and output by a multi-bit quantizer and an associated delta-sigma modulator.
In a typical delta-sigma modulator, the bit number of the internal quantizer is usually the same as that of the feedback digital-to-analog converter (DAC) input. While the bit number of the internal quantizer grows, completing a voltage-to-digital conversion would consume more latency. Ina typical multi-bit quantizer operating in a sequential manner, the most significant bits (MSBs) would be ready first and the least significant bits (LSBs) would be completed with longer latency. Since the LSB information would prolong the loop latency of the delta-signal modulator, implementing a high-speed excess loop delay (ELD) compensation loop path is stringent in a delta-sigma modulator using a multi-bit feedback DAC.